The present invention relates to a semiconductor integrated circuit device, and more particularly to techniques which are effective when applied to the decoder of a read only memory (hereinbelow, abbreviated to "ROM").
One of peripheral LSIs (large-scale integrated circuits) is a graphic data processor (hereinbelow, abbreviated as "GDP") which processes graph data. An instruction program (microprogram) for operating the GDP is set in a microprogram storing ROM (hereinbelow, abbreviated to "micro ROM") which is built in the GDP.
Information is written into the memory cells of the micro ROM by, for example, the following system:
FIGS. 8A and 8B are a plan view and a circuit diagram of the essential portions of the memory cells for explaining the system, respectively. As shown in FIG. 8A, an n.sup.+ -type diffused layer region DF is cut midway at each of the parts of the intersection point between a word line WL.sub.j made of polycrystalline silicon and a bit line BL.sub.j formed of an aluminum film and the intersection point between a similar word line WL.sub.j+1 and a similar bit line BL.sub.j+1. At this part, a thick oxide film LOC (field thermaloxidation film) lies directly under the word line, and in effect, no transistor is formed. The memory cells shown in FIG. 8A are depicted by the circuit diagram of FIG. 8B, in which only two transistors Q.sub.m1 and Q.sub.m2 are existent. In a case where the word line WL.sub.j and the bit line BL.sub.j have been selected, a current path from the bit line BL.sub.j to a ground potential GND is not established because of the absence of any transistor at the intersection point between the lines WL.sub.j and BL.sub.j, so that the potential of the bit line BL.sub.j becomes a high level. In a case where the word line WL.sub.j+1 and the bit line BL.sub.j have been selected, the transistor Q.sub.m2 is turned "on" to establish the current path from the bit line BL.sub.j to the ground potential GND, so that the potential of the bit line BL.sub.j becomes a low level. As understood from FIG. 8A, a contact hole CONT for connecting the bit line and the diffused layer region is shared by two transistors constructing memory cells, so that the writing system is suited to a higher density of integration. Moreover, a mask and a diffusion step for forming the n.sup.+ -type diffused layer regions can be shared by the formation of transistors constituting peripheral circuits, so that any special step for writing information into the ROM is not required. Accordingly, the system is also excellent in the production efficiency of a semiconductor integrated circuit device. A disadvantages of the system is that the period of time (TAT short for "turnaround time") required for the writing of the information into the ROM till the completion of the semiconductor integrated circuit device is rather long. The reason for this is that a photolithographic step employing the mask for forming the n.sup.+ -type diffused layer regions is carried out at a comparatively early stage in an LSI production process.
On the other hand, information in the micro ROM is read out in such a way that address signals received from pairs of complementary address signal lines, each pair consisting of a true line T (e.g. a non-inverting signal line) and a bar line B (e.g. an inverting signal line), are decoded by a decoder, whereby a single word line is selected from among a large number of word lines.
By way of example, the decoder has its cell constructed of an inverter which is configured of a P-channel type MISFET and an N-channel type MISFET, and it has such cells arranged under the corresponding pairs of complementary address signal lines. The gate electrode of the inverter constructing the cell is connected to either the true line T or the bar line B. Here, in a case where the pairs of complementary address signal lines number 11 by way of example, the combinations of the connections of the gate electrodes that can be formed are 2048 in number and depend upon whether these gate electrodes of the inverters of the cells underlying the respective pairs of complementary address signal lines are connected to the true (non-inverting signal) lines or to the bar (inverting signal) lines.
Meanwhile, assuming by way of example that the instruction program has addresses-from Address 1 to Address 1000, the instruction data items of the micro ROM are not always read out in regular order as, for example from Address 1, Address 2, Address 3, ..., but they are read out at random as from Address 1 and then Address 500 or from Address 500 and then Address 100. This aspect differs for every instruction program. Consequently, the order in which the word lines are selected must be changed, so that the circuit arrangement of the decoder is changed. That is, those cells of the decoder whose gate electrodes are connected to the true lines T or to the bar lines B differ depending upon the instruction program. As an example of a measure for coping with this situation, in the micro ROM, the gate electrodes of the cells of the decoder are previously (preliminary) formed so as to extend to under regions where the true lines T are to be formed or regions where the bar lines B are to be formed, at the step of forming these gate electrodes. Thereafter, an interlayer insulator film is formed on the gate electrodes, contact holes are provided in the predetermined parts of the interlayer insulator film, and the true lines T and the bar lines B are formed on the interlayer insulator film including the contact holes. When the gate electrodes are extended to under the true lines T, these true lines are connected to them, and when the gate electrodes are extended to under the bar lines B, these bar lines are connected to them. Thus, the circuit arrangement of the decoder is determined by the step of forming the gate electrodes of the cells.
Although not known, an alternative method of determining the circuit arrangement of the decoder was studied by the inventor. More specifically, a P-channel type MISFET to be connected to the true line T and a P-channel type MISFET to be connected to the bar line B are previously (preliminary) formed separately from each other. Thereafter, one of the P-channel type MISFETs has its threshold voltage changed so as to be inoperable with an ordinary signal level. Thus, the cell of the decoder is configured of the other P-channel type MISFET and the N-channel type MISFET. The threshold voltage of the P-channel type MISFET to be rendered inoperable is changed in the following way: After, for example, the stage at which the interlayer insulator film, the contact holes and the pairs of complementary address signal lines have been formed, the parts of the interlayer insulator film overlying the gate electrodes of the P-channel type MISFETs to be rendered inoperable are selectively removed to form openings, thereby to expose the gate electrodes of these P-channel type MISFETs. Subsequently, an n-type impurity is introduced from the openings into the channel regions of the P-channel type MISFETs through the gate electrodes so as to change the threshold voltages of these MISFETs.